Recent advances in the area of integrated circuit metallization technology have been important in decreasing the necessary chip area for modern integrated circuits. One such advance is the increased number of metal levels that are manufacturable in a device, providing both dramatic reduction in necessary chip area and corresponding dramatic increases in device density. Recent technological advances have also provided significant reductions in the line pitch of conductors in these multiple metal levels, also greatly increasing the functional density of the chip.
As the density of the conductors increases, conventional etches and post-etch cleans used to define the vias or trenches (e.g., the vias or trenches that will ultimately form the conductors) tend to be unacceptable. For example, aggressive post-etch solvent cleans designed to remove unwanted residue from the sidewalls and bottom surface of the vias or trenches prior to the deposition of the conductors, tend to induce unacceptable changes in the desired value for the size of the vias or trenches, or so called critical dimensions (CD's) of the vias or trenches. On the other hand, less aggressive post-etch solvent cleans leave the CD's of the vias or trenches substantially unchanged, however, they also leave undesirable residue which tends to lead to yield loss.
Accordingly, what is needed in the art is a new process for defining openings in a substrate, particularly vias and trenches within dielectric layers, that does not experience the problems of the prior art.